Qualification of the assembly process of flip-chip BGA packages for the next generation synchronous quad data rate sram device to ensure reliability

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Title: Qualification of the assembly process of flip-chip BGA packages for the next generation synchronous quad data rate sram device to ensure reliability
Author: Shivan, Nivetha
Abstract: Quad Data Rate SRAMS (QDR SRAM ) with a maximum speed of 550MHz are the latest technology QDRs in the market . These devices use the traditional wire -bonding interconnects ball grid array package technology with about 165 signal pins . There are next generation QDR SRAMS that are being designed which operates at speeds much higher than 550MHz and signal pins twice as much as that of the present QDRs . These new products would require a new packaging interconnect technology called Flip Chip in order to accommodate higher speed and increased number of signal pins . The reason for this is that Flip Chip shows improved electrical properties over wire -bonding technologies . In this thesis , we deal with the qualification of Flip Chip interconnects technology for a higher pin count device .
URI: http : / /hdl .handle .net /2346 /45324
Date: 2012-05

Citation

Qualification of the assembly process of flip-chip BGA packages for the next generation synchronous quad data rate sram device to ensure reliability. Master's thesis, Texas Tech University. Available electronically from http : / /hdl .handle .net /2346 /45324 .

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