Yield-reliability modeling: application to large processors

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dc.degree.department Electrical and Computer Engineering en_US
dc.degree.discipline Electrical and Computer Engineering en_US
dc.degree.grantor Texas Tech University en_US
dc.degree.level Masters en_US
dc.degree.name M .S .E .E . en_US
dc.rights.availability unrestricted en_US
dc.creator Wilde , Jason Alan en_US
dc.date.accessioned 2014 -02 -19T18 :56 :10Z
dc.date.available 2011 -02 -19T00 :45 :12Z en_US
dc.date.available 2014 -02 -19T18 :56 :10Z
dc.date.issued 2005 -12 en_US
dc.identifier.uri http : / /hdl .handle .net /2346 /22087 en_US
dc.description.abstract This thesis describes an experiment that was performed on a large processor with embedded static random access memory (SRAM ) with built -in redundancy , manufactured using modern very large scale integration (VLSI ) technologies . This experiment will serve to prove the hypothesis that redundant SRAM on a large processor can be used for reliability modeling not only for the SRAM , but also for the functional areas of the device . In order to apply the results of this experiment to production methodology , an existing model that can give the probability of a device failing after it has been repaired using redundant SRAM will be presented and verified . This model can serve as a filter for devices that enter reliability testing , which is costly and time consuming . en_US
dc.language.iso en _US en_US
dc.publisher Texas Tech University en_US
dc.subject defect en_US
dc.subject failure en_US
dc.subject burn in en_US
dc.subject semiconductor en_US
dc.subject killer en_US
dc.subject early en_US
dc.title Yield -reliability modeling : application to large processors en_US
dc.type Electronic Thesis en_US

Citation

Yield-reliability modeling: application to large processors. Master's thesis, Texas Tech University. Available electronically from http : / /hdl .handle .net /2346 /22087 .

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