A multibit cascaded sigma-delta modulator with DAC error cancellation techniques

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Title: A multibit cascaded sigma-delta modulator with DAC error cancellation techniques
Author: Su, Chun-hsien
Abstract: Noise reduction techniques are developed for a multibit cascaded sigma -delta (ÓÄ ) modulator used in the analog interface of a digital signal processing system to improve its performance by reducing the errors introduced by digital -to -analog converters (DACs ) . The idea of the proposed architecture is to create extra feedback paths around the modulator to reduce the DAC errors further by properly designing the error cancellation logic . Transfer functions show that the DAC error at the final stage of the proposed architecture is totally cancelled , while DAC errors from other internal stages are shaped by an order higher than those in a conventional cascaded modulator . The difficulty in circuit implementation of modulators with high resolution and bandwidth increases due to the imperfection of analog components in VLSI processes . Structural and circuit -level compensation techniques are generally used in developing such modulators . Major analog nonideal effects in a multibit cascaded ÓÄ modulator include coefficient mismatches , DAC nonlinearity errors , and integrator leakages . While providing solutions for each of these nonidealities , this dissertation focuses on the minimization of the DAC error since it causes the most performance deterioration . A configurable fourth -order (2 -1 -1 ) ÓÄ modulator is implemented for architecture verification . This modulator can be configured as the proposed architecture as well as a conventional cascaded structure with various modulator orders . The design of the system's parameters and analog blocks are fully described in this dissertation . The system is fabricated by the AMI Semiconductor (AMIS ) 0 .5ìm double -poly triple -metal mixed - signal process through the MOSIS service . Measurement results show that with on -chip error of ±0 .15 LSB for each DAC and an oversampling ratio (OSR ) of 32 , an improvement of 8dB of the proposed architecture over the conventional structure is observed .
URI: http : / /hdl .handle .net /2346 /19955
Date: 2004-05


A multibit cascaded sigma-delta modulator with DAC error cancellation techniques. Doctoral dissertation, Texas Tech University. Available electronically from http : / /hdl .handle .net /2346 /19955 .

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