| dc.date |
2012 -06 -01T14 :16 :14Z |
|
| dc.date |
2007 -05 |
|
| dc.date.accessioned |
2012 -11 -19T22 :26 :59Z |
|
| dc.date.available |
2012 -11 -19T22 :26 :59Z |
|
| dc.date.issued |
2012 -11 -19 |
|
| dc.identifier |
http : / /hdl .handle .net /2346 /17931 |
|
| dc.identifier.uri |
http : / /hdl .handle .net /2346 /17931 |
|
| dc.description |
A yield of 99 % is a very demanding yet achievable target in the semiconductor industry . High volumes and fierce competition call for constant yield management . Continual monitoring of trends and process improvements aim to achieve such high yields . This thesis outlines a systematic approach to problem solving intended to serve as a guide to diagnose and solve yield issues . It also helps identify dead -ends to make pragmatic decisions in view of return on investment . An example problem of yield loss of an Analog to Digital Converter test is discussed to illustrate the procedure . Further , the steps taken to bring its yield up to a satisfying figure are explained . |
|
| dc.format |
application /pdf |
|
| dc.language |
eng |
|
| dc.rights |
Unrestricted . |
|
| dc.subject |
Analog to Digital Converter |
|
| dc.subject |
Problem Solving |
|
| dc.subject |
Yield |
|
| dc.title |
Yield improvement for analog to digital converter test |
|
| dc.type |
Thesis |
|