Yield improvement for analog to digital converter test

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dc.contributor.committeeChair Parten , Michael E .
dc.contributor.committeeMember Nutter , Brian S .
dc.contributor.committeeMember Gale , Richard
dc.degree.department Electrical and Computer Engineering
dc.degree.discipline Electrical and Computer Engineering
dc.degree.grantor Texas Tech University
dc.degree.level Masters
dc.degree.name Master of Science in Electrical Engineering
dc.rights.availability Unrestricted .
dc.creator Kamalapuri , Poorvaja
dc.date.accessioned 2014 -02 -18T22 :09 :21Z
dc.date.available 2012 -06 -01T14 :16 :14Z
dc.date.available 2014 -02 -18T22 :09 :21Z
dc.date.issued 2007 -05
dc.identifier.uri http : / /hdl .handle .net /2346 /17931
dc.description.abstract A yield of 99 % is a very demanding yet achievable target in the semiconductor industry . High volumes and fierce competition call for constant yield management . Continual monitoring of trends and process improvements aim to achieve such high yields . This thesis outlines a systematic approach to problem solving intended to serve as a guide to diagnose and solve yield issues . It also helps identify dead -ends to make pragmatic decisions in view of return on investment . An example problem of yield loss of an Analog to Digital Converter test is discussed to illustrate the procedure . Further , the steps taken to bring its yield up to a satisfying figure are explained .
dc.format.mimetype application /pdf
dc.language.iso eng
dc.subject Analog to Digital Converter
dc.subject Problem Solving
dc.subject Yield
dc.title Yield improvement for analog to digital converter test
dc.type Thesis


Yield improvement for analog to digital converter test. Master's thesis, Texas Tech University. Available electronically from http : / /hdl .handle .net /2346 /17931 .

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