Yield improvement for analog to digital converter test

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Title: Yield improvement for analog to digital converter test
Author: Kamalapuri, Poorvaja
Abstract: A yield of 99 % is a very demanding yet achievable target in the semiconductor industry . High volumes and fierce competition call for constant yield management . Continual monitoring of trends and process improvements aim to achieve such high yields . This thesis outlines a systematic approach to problem solving intended to serve as a guide to diagnose and solve yield issues . It also helps identify dead -ends to make pragmatic decisions in view of return on investment . An example problem of yield loss of an Analog to Digital Converter test is discussed to illustrate the procedure . Further , the steps taken to bring its yield up to a satisfying figure are explained .
URI: http : / /hdl .handle .net /2346 /17931
Date: 2007-05

Citation

Yield improvement for analog to digital converter test. Master's thesis, Texas Tech University. Available electronically from http : / /hdl .handle .net /2346 /17931 .

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