| dc.description |
This thesis describes an experiment that was performed on a large processor with embedded static random access memory (SRAM ) with built -in redundancy , manufactured using modern very large scale integration (VLSI ) technologies . This experiment will serve to prove the hypothesis that redundant SRAM on a large processor can be used for reliability modeling not only for the SRAM , but also for the functional areas of the device . In order to apply the results of this experiment to production methodology , an existing model that can give the probability of a device failing after it has been repaired using redundant SRAM will be presented and verified . This model can serve as a filter for devices that enter reliability testing , which is costly and time consuming . |
|