Yield-reliability modeling: Application to large processors

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dc.contributor.committeeChair Parten , Micheal Eugene
dc.contributor.committeeMember Nutter , Brian S .
dc.degree.department Electrical and Computer Engineering
dc.degree.discipline Electrical and Computer Engineering
dc.degree.grantor Texas Tech University
dc.degree.level Masters
dc.degree.name Master of Science in Electrical Engineering
dc.rights.availability Unrestricted .
dc.creator Wilde , Jason
dc.date.accessioned 2014 -06 -06T20 :18 :33Z
dc.date.available 2012 -06 -01T15 :47 :07Z
dc.date.available 2014 -06 -06T20 :18 :33Z
dc.date.issued 2005 -12
dc.identifier.uri http : / /hdl .handle .net /2346 /1388
dc.description.abstract This thesis describes an experiment that was performed on a large processor with embedded static random access memory (SRAM ) with built -in redundancy , manufactured using modern very large scale integration (VLSI ) technologies . This experiment will serve to prove the hypothesis that redundant SRAM on a large processor can be used for reliability modeling not only for the SRAM , but also for the functional areas of the device . In order to apply the results of this experiment to production methodology , an existing model that can give the probability of a device failing after it has been repaired using redundant SRAM will be presented and verified . This model can serve as a filter for devices that enter reliability testing , which is costly and time consuming .
dc.format.mimetype application /pdf
dc.language.iso eng
dc.subject Semiconductor
dc.subject Burn In
dc.subject Failure
dc.subject Defect
dc.subject Killer
dc.title Yield -reliability modeling : Application to large processors
dc.type Thesis


Yield-reliability modeling: Application to large processors. Master's thesis, Texas Tech University. Available electronically from http : / /hdl .handle .net /2346 /1388 .

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