| dc.contributor.advisor |
Abraham , Jacob A . |
|
| dc.contributor.committeeMember |
Wang , Xianyao |
|
| dc.creator |
Wolfe , Brandon Ward |
|
| dc.date.accessioned |
2012 -02 -27T16 :10 :20Z |
|
| dc.date.available |
2012 -02 -27T16 :10 :20Z |
|
| dc.date.created |
2011 -12 |
|
| dc.date.issued |
2012 -02 -27 |
|
| dc.date.submitted |
December 2011 |
|
| dc.identifier.uri |
http : / /hdl .handle .net /2152 /ETD -UT -2011 -12 -4810 |
|
| dc.description.abstract |
This report is a study of the effects of a commercial 0 .13[mu] process and automotive temperature corners on a synchronous DC -DC buck converter design . The basics of switching converters will be explored with an emphasis on voltage -mode controlled feedback . A Type -III compensation network is designed using transfer function analysis to compensate for the inherent double pole introduced by an LC network . The output of the compensation network will drive a pulse width modulation comparator to vary the duty cycle of the high -side PMOS and low -side NMOS transistor switches . After the synchronous buck converter design was complete , the effect of process and temperature on efficiency , output voltage ripple , inductor peak to peak current , and output voltage load response was examined . |
|
| dc.format.mimetype |
application /pdf |
|
| dc.language.iso |
eng |
|
| dc.subject |
Synchronous buck converter |
|
| dc.subject |
Voltage mode control |
|
| dc.subject |
CMOS switches |
|
| dc.subject |
0 .13[mu] process |
|
| dc.subject |
Pulse width modulation |
|
| dc.title |
Voltage -mode controlled synchronous DC -DC buck converter using 0 .13[mu] CMOS switches |
|
| dc.description.department |
Electrical and Computer Engineering |
|
| dc.type.genre |
thesis |
* |
| dc.type.material |
text |
* |
| thesis.degree.name |
Master of Science in Engineering |
|
| thesis.degree.level |
Masters |
|
| thesis.degree.discipline |
Electrical and Computer Engineering |
|
| thesis.degree.grantor |
University of Texas at Austin |
|
| thesis.degree.department |
Electrical and Computer Engineering |
|
| dc.date.updated |
2012 -02 -27T16 :10 :27Z |
|
| dc.identifier.slug |
2152 /ETD -UT -2011 -12 -4810 |
|