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Abstract:
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As the semiconductor technology roadmap further extends , the development of next generation silicon systems becomes critically challenged . On the one hand , design and manufacturing closures become much more difficult due to the widening gap between the increasing integration density and the limited manufacturing capability . As a result , manufacturability issues become more and more critically challenged in the design of reliable silicon systems . On the other hand , the continuous scaling of feature size imposes critical issues on traditional interconnect materials (Cu /Low -K dielectrics ) due to power , delay and bandwidth concerns . As a result , multiple classes of new materials are under research and development for future generation technologies .
In this dissertation , we investigate several critical Computer -Aided Design (CAD ) challenges under advanced nanolithography and nanophotonics technologies . In addressing these challenges , we propose systematic CAD methodologies and optimization techniques to assist the design of high -yield and high -performance integrated circuits (IC ) with low power consumption .
In Very Large Scale Integration (VLSI ) CAD for nanolithography , we study the manufacturing variability under resolution enhancement techniques (RETs ) and explore two important topics : (1 ) fast and high fidelity lithography hotspot detection ; (2 ) generic and efficient manufacturability aware physical design . For the first topic , we propose a number of CAD optimization and integration techniques to achieve the following goals in detecting lithography hotspots : (a ) high hotspot detection accuracy ; (b ) low false -positive rate (hotspot false -alarms ) ; (c ) good capability to trade -off between detection accuracy and false -alarms ; (d ) fast CPU run -time ; and (e ) excellent layout coverage and computation scalability as design gets more complex . For the second topic , we explore the routing stage by incorporating post -RET manufacturability models into the mathematical formulation of a detailed router to achieve : (a ) significantly reduced lithography -unfriendly patterns ; (b ) small CPU run -time overhead ; and (c ) formulation generality and compatibility to all types of RETs and evoling manufacturing conditions .
In VLSI CAD for nanophotonics , we focus on three topics : (1 ) characterization and evaluation of standard on -chip nanophotonics devices ; (2 ) low power planar routing for on -chip opto -electrically interconnected systems ; (3 ) power -efficient and thermal -reliable design of nanophotonics Wavelength Division Multiplexing for ultra -high bandwidth on -chip communication .
With simulations and experiments , we demonstrate the critical role and effectiveness of Computer -Aided Design techniques as the semiconductor industry marches forward in the deeper sub -micron (45nm and below ) domain . |