E³ : energy-efficient EDGE architectures

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Title: E³ : energy-efficient EDGE architectures
Author: Govindan, Madhu Sarava
Abstract: Increasing power dissipation is one of the most serious challenges facing designers in the microprocessor industry . Power dissipation , increasing wire delays , and increasing design complexity have forced industry to embrace multi -core architectures or chip multiprocessors (CMPs ) . While CMPs mitigate wire delays and design complexity , they do not directly address single -threaded performance . Additionally , programs must be parallelized , either manually or automatically , to fully exploit the performance of CMPs . Researchers have recently proposed an architecture called Explicit Data Graph Execution (EDGE ) as an alternative to conventional CMPs . EDGE architectures are designed to be technology -scalable and to provide good single -threaded performance as well as exploit other types of parallelism including data -level and thread -level parallelism . In this dissertation , we examine the energy efficiency of a specific EDGE architecture called TRIPS Instruction Set Architecture (ISA ) and two microarchitectures called TRIPS and TFlex that implement the TRIPS ISA . TRIPS microarchitecture is a first -generation design that proves the feasibility of the TRIPS ISA and distributed tiled microarchitectures . The second -generation TFlex microarchitecture addresses key inefficiencies of the TRIPS microarchitecture by matching the resource needs of applications to a composable hardware substrate . First , we perform a thorough power analysis of the TRIPS microarchitecture . We describe how we develop architectural power models for TRIPS . We then improve power -modeling accuracy using hardware power measurements on the TRIPS prototype combined with detailed Register Transfer Level (RTL ) power models from the TRIPS design . Using these refined architectural power models and normalized power modeling methodologies , we perform a detailed performance and power comparison of the TRIPS microarchitecture with two different processors : 1 ) a low -end processor designed for power efficiency (ARM /XScale ) and 2 ) a high -end superscalar processor designed for high performance (a variant of Power4 ) . This detailed power analysis provides key insights into the advantages and disadvantages of the TRIPS ISA and microarchitecture compared to processors on either end of the performance -power spectrum . Our results indicate that the TRIPS microarchitecture achieves 11 .7 times better energy efficiency compared to ARM , and approximately 12 % better energy efficiency than Power4 , in terms of the Energy -Delay -Squared (ED² ) metric . Second , we evaluate the energy efficiency of the TFlex microarchitecture in comparison to TRIPS , ARM , and Power4 . TFlex belongs to a class of microarchitectures called Composable Lightweight Processors (CLPs ) . CLPs are distributed microarchitectures designed with simple cores and are highly configurable at runtime to adapt to resource needs of applications . We develop power models for the TFlex microarchitecture based on the validated TRIPS power models . Our quantitative results indicate that by better matching execution resources to the needs of applications , the composable TFlex system can operate in both regimes of low power (similar to ARM ) and high performance (similar to Power4 ) . We also show that the composability feature of TFlex achieves a signification improvement (2 times ) in the ED² metric compared to TRIPS . Third , using TFlex as our experimental platform , we examine the efficacy of processor composability as a potential performance -power trade -off mechanism . Most modern processors support a form of dynamic voltage and frequency scaling (DVFS ) as a performance -power trade -off mechanism . Since the rate of voltage scaling has slowed significantly in recent process technologies , processor designers are in dire need of alternatives to DVFS . In this dissertation , we explore processor composability as an architectural alternative to DVFS . Through experimental results we show that processor composability achieves almost as good performance -power trade -offs as pure frequency scaling (no changes in supply voltages ) , and a much better performance -power trade -off compared to voltage and frequency scaling (both supply voltage and frequency change ) . Next , we explore the effects of additional performance -improving techniques for the TFlex system on its energy efficiency . Researchers have proposed a variety of techniques for improving the performance of the TFlex system . These include : (1 ) block mapping techniques to trade off intra -block concurrency with communication across the operand network ; (2 ) predicate prediction and (3 ) operand multi -cast /broadcast mechanism . We examine each of these mechanisms in terms of its effect on the energy efficiency of TFlex , and our experimental results demonstrate the effects of operand communication , and speculation on the energy efficiency of TFlex . Finally , this dissertation evaluates a set of fine -grained power management (FGPM ) policies for TFlex : instruction criticality and controlled speculation . These policies rely on a temporally and spatially fine -grained dynamic voltage and frequency scaling (DVFS ) mechanism for improving power efficiency . The instruction criticality policy seeks to improve power efficiency by mapping critical computation in a program to higher performance -power levels , and by mapping non -critical computation to lower performance -power levels . Controlled speculation policy , on the other hand , maps blocks that are highly likely to be on correct execution path in a program to higher performance levels , and the other blocks to lower performance levels . Our experimental results indicate that idealized instruction criticality and controlled speculation policies improve the operating range and flexibility of the TFlex system . However , when the actual overheads of fine -grained DVFS , especially energy conversion losses of voltage regulator modules (VRMs ) , are considered the power efficiency advantages of these idealized policies quickly diminish . Our results also indicate that the current conversion efficiencies of on -chip VRMs need to improve to as high as 95 % for the realistic policies to be feasible .
URI: http : / /hdl .handle .net /2152 /ETD -UT -2010 -08 -1934
Date: 2010-12-13

Citation

E³ : energy-efficient EDGE architectures. Doctoral dissertation, University of Texas at Austin. Available electronically from http : / /hdl .handle .net /2152 /ETD -UT -2010 -08 -1934 .

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