Techniques for reducing power dissipation during scan testing

This dissertation addresses the problem of excessive power dissipation during scan testing. High power dissipation problems can be classified into two types: high average power dissipation and high peak power dissipation. New techniques are presented in this dissertation to deal with both kinds of problems. All steps in a typical test generation and application flow were looked at for opportunities to reduce power consumption during testing. Five techniques are presented in this dissertation. A heuristic technique for static test vector compaction is presented, which can be applied very early in the test flow. A technique to modify vectors to reduce peak power, which can be applied after test pattern generation has been completed, is presented. This method requires no changes to the test generation software or to the circuit-under-test. Two simple design-for-test techniques that can be used to reduce peak power are presented. These techniques require modifications to the circuit-under-test. A vector- modification technique that can be applied to circuits having scan chains with separate clocks (a common case) is presented. This is a middle-ground technique in which an existing feature of the circuit-under-test is exploited to reduce power consumption during testing.