|
Abstract:
|
The research investigates several critical design issues of continuous -time (CT ) [Sigma Delta] modulators . The first is to investigate the sensitivity of CT [Sigma Delta] modulators to high -frequency clock spurs . These spurs down -convert the high -frequency quantization noise , degrading the dynamic range of the modulator . The second is to study the robustness of continuous -time loop filters under large RC product variations . Large RC variations in the CMOS process strongly degrade the performance of continuous -time [Sigma Delta] modulators , and reduce the production yield . The third is to model the harmonic distortion of one -bit continuous -time [Sigma Delta] modulators due to the interaction between the first integrator and the feedback digital -to -analog converter (DAC ) . A closed -form expression of the 3'rd -order harmonic distortion is derived and verified . Conventional CT [Sigma Delta] modulators employ all active integrators : each integrator needs an active amplifier . The research proposes a 5th -order continuous -time [Sigma Delta] modulator with a hybrid active -passive loop filter consisting of only three amplifiers . The passive integrators save power , and introduce no distortion . The active integrators provide gain and minimize internal noise contributions . A single -bit switched -capacitor DAC is employed as the main feedback DAC for high clock jitter immunity . An additional current steering DAC stabilizes the loop with the advantage of simplicity . To verify the proposed techniques , a prototype continuous -time [Sigma Delta] modulator with 2 -MHz signal bandwidth is designed in a 0 .25 -¹m CMOS technology targeting for GPS or WCDMA applications . The experimental results show that the prototype modulator achieves 68 -dB dynamic range over 2 -MHz bandwidth with a 150 -MHz clock , consuming 1 .8 mA from a 1 .5 -V supply . |