Parallel multipliers for modular arithmetic

Modular multiplication is a core operation in virtually all public-key cryptosystems in use today. In this research, parallel, high-speed designs for modular multiplication are presented. These high speed designs take advantage of the transistor bounty provided by Moore’s law and the continuously diminishing average cost of a transistor. In addition, advances in Computer-Aided Design (CAD) synthesis are leveraged to explore designs that are otherwise difficult to manually layout. Novel parallel algorithms and high-speed multipliers for prime and extension Galois fields are presented in this work. A tool is developed that automatically generates Hardware Description Language (HDL) code for the various designs. Simulation is used to evaluate the area and delay complexities of all the designs.