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The increasing ubiquity of chip multiprocessor machines has made the need for accessible approaches to parallel programming all the more urgent . The current state of the art , based on threads and locks , requires the programmer to use mutual exclusion to protect shared resources , enforce invariants , and maintain consistency constraints . Despite decades of research effort , this approach remains fraught with difficulty . Lock -based programming is complex and error -prone , largely due to well -known problems such as deadlock , priority inversion , and poor composability . Tradeoffs between performance and complexity for locks remain unattractive . Coarse -grain locking is simple but introduces artificial sharing , needless serialization , and yields poor performance . Fine -grain locking can address these issues , but at a significant cost in complexity and maintainability . Transactional memory has emerged as a technology with the potential to address this need for better parallel programming tools . Transactions provide the abstraction of isolated , atomic execution of critical sections . The programmer specifies regions of code which access shared data , and the system is responsible for executing that code in a way that is isolated and atomic . The programmer need not reason about locks and threads . Transactional memory removes many of the pitfalls of locking : transactions are livelock - and deadlock -free and may be composed freely . Hardware transactional memory , which is the focus of this thesis , provides an efficient implementation of the TM abstraction . This thesis explores several key aspects of supporting hardware transactional memory (HTM ) : operating systems support and integration , architectural , design , and implementation considerations , and programmer -transparent techniques to improve HTM performance in the presence of contention . Using and supporting HTM in an OS requires innovation in both the OS and the architecture , but enables practical approaches and solutions to some long -standing OS problems . Innovations in transactional cache coherence protocols enable HTM support in the presence of multi -level cache hierarchies , rich HTM semantics such as suspend /resume and multiple transactions per thread context , and can provide the building blocks for support of flexible contention management policies without the need to trap to software handlers . We demonstrate a programmer -transparent hardware technique for using dependences between transactions to commit conflicting transactions , and suggest techniques to allow conflicting transactions to avoid performance -sapping restarts without using heuristics such as backoff . Both mechanisms yield better performance for workloads that have significant write -sharing . Finally , in the context of the MetaTM HTM model , this thesis contributes a high -fidelity cross -design comparison of representative proposals from the literature : the result is a comprehensive exploration of the HTM design space that compares the behavior of models of MetaTM (70 , 75 ) , LogTM (58 , 94 ) , and Sun's Rock (22 ) . |
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