Communication synthesis of networks-on-chip (NoC)

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Title: Communication synthesis of networks-on-chip (NoC)
Author: Bhojwani, Praveen Sunder
Abstract: The emergence of networks -on -chip (NoC ) as the communication infrastructure solution for complex multi -core SoCs presents communication synthesis challenges . This dissertation addresses the design and run -time management aspects of communication synthesis . Design reuse and the infeasibility of Intellectual Property (IP ) core interface redesign , requires the development of a Core -Network Interface (CNI ) which allows them to communicate over the on -chip network . The absence of intelligence amongst the NoC components , entails the introduction of a CNI capable of not only providing basic packetization and depacketization , but also other essential services such as reliability , power management , reconguration and test support . A generic CNI architecture providing these services for NoCs is proposed and evaluated in this dissertation . Rising on -chip communication power costs and reliability concerns due to these , motivate the development of a peak power management technique that is both scalable to dierent NoCs and adaptable to varying trac congurations . A scalable and adaptable peak power management technique - SAPP - is proposed and demonstrated . Latency and throughput improvements observed with SAPP demonstrate its superiority over existing techniques . Increasing design complexity make prediction of design lifetimes dicult . Post SoC deployment , an on -line health monitoring scheme , is essential to maintain con - dence in the correct operation of on -chip cores . The rising design complexity and IP core test costs makes non -concurrent testing of the IP cores infeasible . An on -line scheme capable of managing IP core test in the presence of executing applications is essential . Such a scheme ensures application performance and system power budgets are eciently managed . This dissertation proposes Concurrent On -Line Test (COLT ) for NoC -based systems and demonstrates how a robust implementation of COLT using a Test Infrastructure -IP (TI -IP ) can be used to maintain condence in the correct operation of the SoC .
URI: http : / /hdl .handle .net /1969 .1 /85789
Date: 2008-10-10


Communication synthesis of networks-on-chip (NoC). Available electronically from http : / /hdl .handle .net /1969 .1 /85789 .

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