A CMOS 500MHz continuous-time fourth order 0.05degree equiripple linear phase filter with automatic tuning

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dc.contributor.advisor Silva -Martinez , Jose en_US
dc.contributor.committeeMember Sanchez -Sinencio , Edgar en_US
dc.creator Pandey , Pankaj en_US
dc.date.accessioned 2004 -09 -30T01 :41 :26Z
dc.date.accessioned 2014 -02 -18T22 :28 :08Z
dc.date.available 2004 -09 -30T01 :41 :26Z
dc.date.available 2014 -02 -18T22 :28 :08Z
dc.date.created 2003 -05 en_US
dc.date.issued 2004 -09 -30T01 :41 :26Z
dc.identifier.uri http : / /hdl .handle .net /1969 .1 /68
dc.description.abstract The growing demand of portable electronic equipment and system -on -a -chip has been pushing the industry to design circuits with very low power supply voltage and low power consumption . The Hard Disk drive industry is looking for developments in the read channel chip to push the data rates to higher speed , along with a low voltage and low cost solution . Read channel requires high -speed linear phase filters to meet these objectives . The primary objective of this project is to design , layout , and characterize a 4th -order continuous -time equiripple linear phase filter with automatic tuning system . The main requirements for design are high speed , low group delay variations , good linearity and power efficiency . This filter features wide cut -off frequency 500MHz , which is far beyond the current state -of -the -art . The linear phase filter is based on Gm -C biquadratics . Higher speed has been achieved by minimizing the parasitics and a complementary input stage OTA . A common mode feedback (CMFB ) , which ensures stability at such high frequencies , has also been designed . The inaccuracies of the filter are compensated by using a simple automatic tuning system . The design is fabricated in 0 .35 um TSMC CMOS process technology . The design was simulated in Cadence using SPICE models provided by MOSIS for the 0 .35 um TSMC process in the presence of parasitic capacitance and transistor non -idealities . Cut -off frequency of 500 MHz was achieved along with a 9 % variation in the group delay . en_US
dc.format.extent 1299558 bytes
dc.format.medium electronic en_US
dc.format.mimetype application /pdf
dc.language.iso en _US en_US
dc.publisher Texas A &M University en_US
dc.subject Linear en_US
dc.title A CMOS 500MHz continuous -time fourth order 0 .05degree equiripple linear phase filter with automatic tuning en_US
dc.type Book en
dc.type.genre Electronic Thesis en_US
dc.type.material text en_US
dc.format.digitalOrigin born digital en_US

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A CMOS 500MHz continuous-time fourth order 0.05degree equiripple linear phase filter with automatic tuning. Available electronically from http : / /hdl .handle .net /1969 .1 /68 .

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