Integrated circuit outlier identification by multiple parameter correlation

Show full item record

Title: Integrated circuit outlier identification by multiple parameter correlation
Author: Sabade, Sagar Suresh
Abstract: Semiconductor manufacturers must ensure that chips conform to their specifications before they are shipped to customers . This is achieved by testing various parameters of a chip to determine whether it is defective or not . Separating defective chips from fault -free ones is relatively straightforward for functional or other Boolean tests that produce a go /no -go type of result . However , making this distinction is extremely challenging for parametric tests . Owing to continuous distributions of parameters , any pass /fail threshold results in yield loss and /or test escapes . The continuous advances in process technology , increased process variations and inaccurate fault models all make this even worse . The pass /fail thresholds for such tests are usually set using prior experience or by a combination of visual inspection and engineering judgment . Many chips have parameters that exceed certain thresholds but pass Boolean tests . Owing to the imperfect nature of tests , to determine whether these chips (called "outliers" ) are indeed defective is nontrivial . To avoid wasted investment in packaging or further testing it is important to screen defective chips early in a test flow . Moreover , if seemingly strange behavior of outlier chips can be explained with the help of certain process parameters or by correlating additional test data , such chips can be retained in the test flow before they are proved to be fatally flawed . In this research , we investigate several methods to identify true outliers (defective chips , or chips that lead to functional failure ) from apparent outliers (seemingly defective , but fault -free chips ) . The outlier identification methods in this research primarily rely on wafer -level spatial correlation , but also use additional test parameters . These methods are evaluated and validated using industrial test data . The potential of these methods to reduce burn -in is discussed .
URI: http : / /hdl .handle .net /1969 .1 /267
Date: 2004-09-30

Citation

Integrated circuit outlier identification by multiple parameter correlation. Available electronically from http : / /hdl .handle .net /1969 .1 /267 .

Files in this item

Files Size Format View
etd-tamu-2004A-CPEN-Sabade-1.pdf 6.428Mb application/pdf View/Open

This item appears in the following Collection(s)

Show full item record

Search DSpace

Advanced Search

Browse