Exploiting level sensitive latches in wire pipelining

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Title: Exploiting level sensitive latches in wire pipelining
Author: Seth, Vikram
Abstract: The present research presents procedures for exploitation of level sensitive latches in wire pipelining . The user gives a Steiner tree , having a signal source and set of destination or sinks , and the location in rectangular plane , capacitive load and required arrival time at each of the destinations . The user also defines a library of non -clocked (buffer ) elements and clocked elements (flip -flop and latch ) , also known as synchronous elements . The first procedure performs concurrent repeater and synchronous element insertion in a bottom -up manner to find the minimum latency that may be achieved between the source and the destinations . The second procedure takes additional input (required latency ) for each destination , derived from previous procedure , and finds the repeater and synchronous element assignments for all internal nodes of the Steiner tree , which minimize overall area used . These procedures utilize the latency and area advantages of latch based pipelining over flip -flop based pipelining . The second procedure suggests two methods to tackle the challenges that exist in a latch based design . The deferred delay padding technique is introduced , which removes the short path violations for latches with minimal extra cost .
URI: http : / /hdl .handle .net /1969 .1 /1433
Date: 2005-02-17

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Exploiting level sensitive latches in wire pipelining. Available electronically from http : / /hdl .handle .net /1969 .1 /1433 .

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