1/f Noise In Hafnium Based High-k Gate Dielectric MOSFETS And A Review Of Modeling

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dc.contributor Devireddy , Siva Prasad en_US
dc.date.accessioned 2008 -04 -22T02 :41 :11Z
dc.date.accessioned 2011 -08 -24T21 :41 :05Z
dc.date.available 2008 -04 -22T02 :41 :11Z
dc.date.available 2011 -08 -24T21 :41 :05Z
dc.date.issued 2008 -04 -22T02 :41 :11Z
dc.date.submitted August 2007 en_US
dc.identifier.uri http : / /hdl .handle .net /10106 /681
dc.description.abstract For next generation MOSFETs , the constant field scaling rule dictates a reduction in the gate oxide thickness among other parameters . Consequently , gate leakage current becomes a serious issue with very thin SiO2 that is conventionally used as gate dielectric since it is the native oxide for Si substrate . This has driven an industry wide search for suitable alternate 'high -k' gate dielectric that has a high value of relative permittivity compared to SiO2 thereby presenting a physically thicker barrier for tunneling carriers while providing a high gate capacitance . Consequently , it is essential to study the properties of these novel materials and the interfaces that they form with the substrate , gate or other dielectrics in a multi -level stack . The main focus of this work is the 1 /f noise that is specifically used as a characterization tool to evaluate the performance of high -k MOSFETs . Nevertheless , DC and split C -V characterization are done as well to obtain device performance parameters that are used in the noise analysis . At first , the room temperature 1 /f noise characteristics are presented for n - and p -channel poly -Si gated MOSFETs with three different gate dielectrics - HfO2 , Al2O3 (top layer ) /HfO2 (bottom layer ) , HfAlOx . The devices had either 1 nm or 4 nm SiO2 interfacial layer , thus presenting an opportunity to understand the effects of interfacial layer thickness on noise and carrier mobility . In the initial study , the analysis of noise is done based on the Unified Flicker Noise Model . Next , a comparative study of 1 /f noise behavior is presented for TaSiN (NMOS ) and TiN (PMOS ) gated MOSFETs with HfO2 gate dielectric and their poly -Si gated counterparts . Additionally , in TaSiN MOSFETs , the effect of the different deposition methods employed for interfacial layer formation on the overall device performance is studied . Finally , the 'Multi -Stack Unified Noise' model (MSUN ) is proposed to better model /characterize the 1 /f noise in multi -layered high -k MOSFETs . This model takes the non -uniform trap density profile and other physical properties of the constituent gate dielectrics into account . The MSUN model is shown to be in excellent agreement with the experimental data obtained on TaSiN /HfO2 /SiO2 MOSFETs in the 78 -350 K range . Additionally , the MSUN model is expressed in terms of surface potential based parameters for inclusion in to the circuit simulators . en_US
dc.language.iso EN en_US
dc.publisher Electrical Engineering en_US
dc.title 1 /f Noise In Hafnium Based High -k Gate Dielectric MOSFETS And A Review Of Modeling en_US
dc.type Ph .D . en_US


1/f Noise In Hafnium Based High-k Gate Dielectric MOSFETS And A Review Of Modeling. Available electronically from http : / /hdl .handle .net /10106 /681 .

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