Fabrication Of A Silicon Single Electron Transistor

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dc.contributor Chinoy , Sharukh Roomy en_US
dc.date.accessioned 2007 -09 -17T17 :07 :32Z
dc.date.accessioned 2011 -08 -24T21 :40 :55Z
dc.date.available 2007 -09 -17T17 :07 :32Z
dc.date.available 2011 -08 -24T21 :40 :55Z
dc.date.issued 2007 -09 -17T17 :07 :32Z
dc.date.submitted August 2007 en_US
dc.identifier.uri http : / /hdl .handle .net /10106 /600
dc.description.abstract Single electronics has bright prospects because of its high scalability . The single electron transistor (SET ) which utilizes these principles could replace the current workhorse of the industry , the MOSFET . The SET is plagued with limitations such as , a low operating temperature , background charge issues , a low voltage gain and high output impedance . The current generation SET devices have overcome most of the aforementioned issues but use highly complicated fabrication techniques . Electron beam lithography was used to pattern device structures on silicon -on -insulator (SOI ) wafers with a hydrogen silsesquioxane (HSQ ) system being the resist . The silicon was then etched using HSQ as the mask in a deep reactive ion etcher with SF6 and O2 gasses . Experimentation was also carried out on other electron beam resists namely UVN30 and PMMA ; these were incompatible with my fabrication technique due to their resolution capability and etch resistance respectively . en_US
dc.language.iso EN en_US
dc.publisher Electrical Engineering en_US
dc.title Fabrication Of A Silicon Single Electron Transistor en_US
dc.type M .S . en_US

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Fabrication Of A Silicon Single Electron Transistor. Available electronically from http : / /hdl .handle .net /10106 /600 .

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