Thermal Enhancement Of Stacked Dies Using Thermal Vias

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Title: Thermal Enhancement Of Stacked Dies Using Thermal Vias
Author: Sung, Baekyoung
Abstract: Following Moore's law , the number of transistors on a die continues to rise and has recently exceeded a billion on high end processors . In light of the convergence of technology , power requirements is becoming a serious concern even on low density interconnect systems such as cellular phones and personal digital assistants . Also , in order to minimize foot prints , the recent trend in packaging is stacking . The stacking , however , creates challenges in cooling and especially if one is to include logic in the stack . The primary heat flow path for stacking is through the substrate and as the number of stacks increase , the cooling problem is amplified . Thermal vias are emerging as a viable technology for transferring heat and in effect creating a thermal short circuit from individual die to the substrate . This thesis focuses on enhancement of thermal vias in different stacked die architectures for flash semiconductor products . Three different die stacking architectures were drawn as follows : spacer stacked , rotated stacked and pyramid stacked die . Geometries were drawn by using Pro -Engineer Wildfire 2 .0 as a Computer -Aided -Design tool and imported to Ansys Workbench 10 .0 , where meshed analysis was conducted . There are different number thermal vias every packaging . So , this thesis compares the junction temperature and heat flux as number of thermal vias .
URI: http : / /hdl .handle .net /10106 /5
Date: 2007-08-23

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Thermal Enhancement Of Stacked Dies Using Thermal Vias. Available electronically from http : / /hdl .handle .net /10106 /5 .

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